The VHDL code relative to the shift register implementation above has been layout using Intel Quartus II v 13 web edition It is less intuitive but very elegant and compact. In this case, we can describe a shift register with a The third approach takes advantage of the It is simple to read and understand, and it is parametrizable. The second approach uses the for-loop VHDL
#SERIAL ADDER VHDL HOW TO#
In this post, we clarified how to implementĪ shift-register in VHDL using three different approaches. Of course, pay attention, you can fill anĪs clear from Figure5 the single line VHDL shift register implementation produce the same output of the other two shift register description. If you need to describe a very huge shift-register you can do it with a single VHDL line of code!
#SERIAL ADDER VHDL FULL#
Figure 5 shift register description#4 using single line VHDL code RTL viewĪs you can see this shift-register description take full advantage of VHDL power description. The VHDL allow assigning object of the same type in a single line of code.įor instance, you cannot perform the same assignment in C. In this description, the shift functionality is implemented using the assignment feature provided by VHDL. R_data <= i_data&r_data(0 to r_data'length-2)
Type t_sreg is array(0 to 3) of std_logic_vector(1 downto 0) In the VHDL code, we used a type declaration for the shift register so the number of shift registers to be implemented can be passed as constant or generic in the VHDL entity. With respect to the shift register plainĭescription, the VHDL for-loop implementation can be parametrized. Implementation, in terms of VHDL code description, can be achieved usingįor-loop iterative statement. For the variable the value is assigned immediately, it is not scheduled and it is performed immediately. In the case of shift-register implemented using variables, you must pay attention to the assignment order. It is a way to encapsulate the code, something like a component instantiation. So, you can use always the same process implementing a different set of shift-registers. This approach is useful when you need different shift-register avoiding the declaration of a lot of signals.Īs you know, the variables are local to the process where you declare them. description#2 VHDL code for shift register implemented using variableįigure 2 shift register description#1 using signal RTL view Figure 3 shift register description#2 using variable RTL view.description #1 VHDL code for shift register implemented using signal.the two VHDL codes implement the same hardware. In Figure 2 and Figure 3 are reported a layout example of Shift register VHDL description #1 and description#2. Signal r3_data : std_logic_vector(1 downto 0) Signal r2_data : std_logic_vector(1 downto 0) Signal r1_data : std_logic_vector(1 downto 0) Signal r0_data : std_logic_vector(1 downto 0) O_data : out std_logic_vector(1 downto 0)) I_data : in std_logic_vector(1 downto 0)
The three descriptions are totally equivalent.Ī plain description of the shift registers in Figure 1 is reported in the VHDL code below. Figure 1 shift register architecture exampleĪs stated before, there are at least three different ways to describe such hardware structure in VHDL.
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